1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and more specifically, it relates to a random access memory comprising a memory cell having a magnetic tunnel junction (MTJ).
2. Description of the Prior Art
An MRAM (magnetic random access memory) device is watched with interest as a memory device capable of storing data in a nonvolatile manner with small power consumption. The MRAM device, storing data in a nonvolatile manner with a plurality of thin film magnetic elements formed in a semiconductor integrated circuit, is capable of making random access to each of the thin film magnetic elements.
In particular, it has recently been reported that the performance of an MRAM device is remarkably progressed by employing thin film magnetic elements utilizing magnetic tunnel junctions (MTJ) as memory cells. An MRAM device comprising memory cells having magnetic tunnel junctions is disclosed in technical literature such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, Feb. 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000 or the like.
FIG. 23 is a schematic diagram showing the structure of a memory cell (hereinafter also simply referred to as xe2x80x9cMTJ memory cellxe2x80x9d) having a magnetic tunnel junction part.
Referring to FIG. 23, the MTJ memory cell includes a magnetic tunnel junction part MTJ having a resistance value varying with the level of stored data and an access transistor ATR. The access transistor ATR is formed by a field-effect transistor, and connected between the magnetic tunnel junction part MTJ and a ground voltage Vss.
A write word line WWL for instructing data writing, a read word line RWL for instructing data reading and a bit line BL which is a data line for transmitting an electric signal corresponding to the level of the stored data in data reading and data writing are arranged for the MTJ memory cell.
FIG. 24 is a conceptual diagram illustrating data read operation from the MTJ memory cell.
Referring to FIG. 24, the magnetic tunnel junction part MTJ has a magnetic layer (hereinafter also simply referred to as xe2x80x9cfixed magnetic layerxe2x80x9d) FL having a fixed field of a constant direction and another magnetic layer (hereinafter also simply referred to as xe2x80x9cfree magnetic layerxe2x80x9d) VL having a free field. A tunnel barrier TB formed by an insulator film is arranged between the fixed magnetic layer FL and the free magnetic layer VL. In response to the level of the stored data, either a magnetic field of the same direction as the fixed magnetic layer FL or a magnetic field of a different direction from the fixed magnetic layer FL is written in the free magnetic layer VL in a nonvolatile manner.
In data reading, the access transistor ATR is turned on in response to activation of the read word line RWL. Thus, a sense current Is supplied from a control circuit (not shown) as a constant current flows through a current path along the bit line BL, the magnetic tunnel junction part MTJ, the access transistor ATR and the ground voltage Vss.
The resistance value of the magnetic tunnel junction part MTJ varies with the relation between the field directions of the fixed magnetic layer FL and the free magnetic layer VL. When the field direction of the fixed magnetic layer FL is same to the field direction written in the free magnetic layer VL, the resistance value of the magnetic tunnel junction part MTJ is reduced as compared with the case where the field directions are different from each other.
In data reading, therefore, a voltage drop caused by the sense current Is in the magnetic tunnel junction part MTJ varies with the field direction stored in the free magnetic layer VL. Thus, when starting supplying the sense current Is after temporarily precharging the bit line BL to a high voltage, the level of the data stored in the MTJ memory cell can be read by monitoring change in the voltage level of the bit line BL.
FIG. 25 is a conceptual diagram illustrating data write operation in the MTJ memory cell.
Referring to FIG. 25, the read word line RWL is inactivated and the access transistor ATR is turned off in data writing. In this state, data write currents for writing the magnetic field in the free magnetic layer VL are fed to the write word line WWL and the bit line BL respectively. The field direction of the free magnetic layer VL is decided by the combination of the directions of the data write currents flowing through the write word line WWL and the bit line BL respectively.
FIG. 26 is a conceptual diagram showing the relation between the directions of the data write currents and the field directions in data writing.
Referring to FIG. 26, symbol Hx on the horizontal axis denotes the direction of a magnetic field H(WWL) formed by the data write current flowing through the write word line WWL. Symbol Hy on the vertical axis denotes the direction of a magnetic field H(BL) formed by the data write current flowing through the bit line BL.
The field direction stored in the free magnetic layer VL is newly written only when the sum of the magnetic fields H(WWL) and H(BL) reaches an area outside asteroid characteristic curves shown in FIG. 26. In other words, the field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the area inside the asteroid characteristic curves is applied.
In order to update the data stored in the magnetic tunnel junction part MTJ, therefore, currents must be fed to both of the write word line WWL and the bit line BL. The field direction once stored in the magnetic tunnel junction part MTJ, i.e. the stored data, is held in a nonvolatile manner until new data writing is executed.
Also in data read operation, the sense current Is flows through the bit line BL. However, the sense current Is is generally set to be smaller by one or two orders of magnitude than the aforementioned data write currents, and hence there is a small possibility that the data stored in the MTJ memory cell is erroneously rewritten due to influence by the sense current Is in data reading.
The aforementioned technical literature discloses a technique of integrating such MTJ memory cells on a semiconductor substrate and forming an MRAM device, which is a random access memory.
FIG. 27 is a conceptual diagram showing MTJ memory cells integrated/arranged in rows and columns.
Referring to FIG. 27, a highly integrated MTJ device can be implemented by arranging the MTJ memory cells in rows and columns on a semiconductor substrate. The MTJ memory cells are arranged in n rows by columns (n and m: natural numbers) in FIG. 27.
As described above, the bit line BL, the write word line WWL and the read word line RWL must be arranged for each MTJ memory cell. Therefore, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn and m bit lines BL1 to BLm must be arranged for the n by m MTJ memory cells. Thus, independent word lines are generally provided for MTJ memory cells in correspondence to read operation and write operation respectively.
FIG. 28 is a structural diagram of an MTJ memory cell arranged on a semiconductor substrate.
Referring to FIG. 28, an access transistor ATR is formed on a p-type region PAR of a semiconductor main substrate SUB. The access transistor ATR has source/drain regions 110 and 120, which are n-type regions, and a gate 130. The source/drain region 110 is connected with a ground voltage Vss through a metal wire formed on a first metal wiring layer M1. A metal wire formed on a second metal wiring layer M2 is employed for a write word line WWL. A bit line BL is provided on a third metal wiring layer M3.
A magnetic tunnel junction part MTJ is arranged between the second metal wiring layer M2 provided with the write word line WWL and the third metal wiring layer M3 provided with the bit line BL. The source/drain region 120 of the access transistor ATR is electrically connected with the magnetic tunnel junction part MTJ through a metal film 150 formed in a contact hole, the first and second metal wiring layers M1 and M2 and a barrier metal 140. The barrier metal 140 is a buffering member provided for electrically connecting the magnetic tunnel junction part MTJ with the metal wires.
As described above, the read word line RWL and the write word line WWL are provided independently of each other in the MTJ memory cell. The write word line WWL and the bit line BL must be fed with data write currents for generating magnetic fields exceeding a prescribed value in data writing. Therefore, the bit line BL and the write word line WWL are formed by the metal wires.
On the other hand, the read word line RWL, provided for controlling the gate voltage of the access transistor ATR, may not be positively fed with a current. In consideration of improvement in degree of integration, therefore, the read word line RWL is formed by a polysilicon layer or a polycide structure in the same wiring layer as the gate 130 without newly providing an independent metal wiring layer.
Thus, when integrating and arranging MTJ memory cells on a semiconductor substrate, an additional wiling layer must be provided for write word lines for data writing, disadvantageously leading to increase in fabrication cost resulting from complication of processes following increase of the number of metal wires.
Further, a number of MTJ memory cells belonging to the same column are regularly connected to each of the bit lines BL1 to BLm, to disadvantageously increase the capacitances of the bit lines BL1 to BLm. Consequently, it is difficult to increase the speed of data read operation in particular.
An object of the present invention is to increase the speed of data read operation and reduce the fabrication cost by reducing the number of wiring layers in an MRAM device having MTJ memory cells.
Briefly stated, the present invention is directed to a thin film magnetic memory device comprising a memory array, a plurality of write word lines, a plurality of read word lines and a plurality of data lines. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a storage part having a resistance value varying with the level of stored data written when data write fields applied by first and second data write currents are larger than a prescribed magnetic field, and a memory cell selection gate for passing a data read current through the storage part in data reading. The plurality of write word lines are provided in correspondence to the rows of the magnetic memory cells respectively and selectively activated in response to a result of row selection for feeding the first data write current in data writing. The plurality of read word lines are provided in correspondence to the rows respectively for operating the corresponding memory cell selection gates in response to a result of row selection in the data reading. The plurality of data lines are provided in correspondence to the columns of the magnetic memory cells respectively for feeding the second data write current and the data read current in the data writing and the data reading respectively. Each of the plurality of data lines is electrically connected with the storage parts through the memory cell selection gates in the magnetic memory cells belonging to the corresponding column.
Therefore, a principal advantage of the present invention resides in that only magnetic memory cells corresponding to a row selected as the object of data reading are connected with the data line, whereby the capacitance of the data line can be reduced for performing data reading at a high speed.
A thin film magnetic memory device according to another aspect of the present invention comprises a memory array, a plurality of write word lines, a plurality of read word lines and a plurality of data lines. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a storage part having a resistance value varying with the level of stored data written when data write fields applied by first and second data write currents are larger than a prescribed magnetic field and a memory cell selection gate for passing a data read current through the storage part in data reading. The plurality of write word lines are provided in correspondence to the rows of the magnetic memory cells respectively, and selectively activated in response to a result of row selection for feeding the first data write current in data writing. Each of the plurality of write word lines is electrically connected with the storage parts through the memory cell selection gates in the magnetic memory cells belonging to the corresponding column, and inactivated and set to a prescribed voltage in the data reading. The plurality of read word lines are provided in correspondence to the rows respectively for operating the corresponding memory cell selection gates in response to a result of row selection in the data reading. The plurality of data lines are provided in correspondence to the columns of the magnetic memory cells respectively for feeding the second data write current and the data read current in the data writing and the data reading respectively. The voltage levels of the plurality of data lines are set to a voltage different from the prescribed voltage before execution of the data reading.
Therefore, a path for the data read current can be ensured by connecting the storage parts with the prescribed voltage by the write word lines in data reading, whereby the thin film magnetic memory device can be formed on a semiconductor substrate with a smaller number of metal wiring layers.
A thin film magnetic memory device according to still another aspect of the present invention comprises a memory array, a plurality of write word lines, a plurality of read word lines, a plurality of write data lines and a plurality of read data lines. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each of the plurality of magnetic memory cells includes a storage part having a resistance value varying with the level of stored data written when data write fields applied by first and second data write currents are larger than a prescribed magnetic field and a memory cell selection gate for passing a data read current through the storage part in data reading. The plurality of write word lines are provided in correspondence to the rows of the magnetic memory cells respectively, and selectively activated in response to a result of row selection for feeding the first data write current in data writing. The plurality of read word lines are provided in correspondence to the rows respectively for operating the corresponding memory cell selection gates in response to a result of row selection in the data reading. The plurality of write data lines are provided in correspondence to the columns of the magnetic memory cells respectively for feeding the second data write current in the data writing. The plurality of read data lines are provided in correspondence to the columns respectively for feeding the data read current in the data reading. Each of the plurality of read data lines is electrically connected with each of the storage parts belonging to the corresponding column through the memory cell selection gate.
Therefore, only the magnetic memory cells corresponding to the row selected as the object of data reading are connected with the read data line in the structure capable of efficiently executing data reading and data writing by independently arranging the read data lines and the write data lines, whereby the capacitances of the read data lines can be reduced for performing data reading at a high speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.